Dynamic Model of Switched-Capacitor DC–DC Converters in the Slow-Switching Limit Including Charge Reusing

Abstract

A reliable model to analyze the dynamic behavior of two-phase switched-capacitor dc-dc converters in the slow-switching limit regime is proposed, taking into account both top and bottom parasitic capacitances as well as the charge reusing approach. This technique features significant improvements in both gain and efficiency with respect to existing solutions. We calculate the slow-switching limit boundary layer taking into account the parasitic capacitances of the flying capacitors and the dynamic and parasitic effects from the switches. The model is highly reliable into this region, featuring better accuracy in both time response and charge consumed than previous models in the literature. Also, as we will show that it can be used outside this region assuming a certain accuracy loss. The model is verified by experimental results and circuit-level simulations. The model has been implemented in an open-access web simulator, saving up to 10 000× in computation time when compared to well-known circuit-level simulators. The applicability of the model is illustrated through the optimization of charge efficiency and time response in a typical situation for light microenergy harvesting using Dickson, Fibonacci, and exponential solutions