5-Bit Signed SRAM-Based In-Memory Computing Cell

Abstract

Hardware accelerators are critical in providing real-time processing for edge computing applications, particu-larly in the context of convolutional neural networks. A crucial challenge in this context is achieving low power consumption while maintaining an appropriate performance in terms of accuracy. This work delves into a thorough analysis of prospective architectures for the core cell of the multiply -and -accumulate function, monitoring each structure's crucial benefits and drawbacks. It includes electrical simulations comparing their performance in a 180 nm process node for 1.8 V and 3.3 V. Moreover, a process corner simulation is proposed to identify on-chip process variations in the voltage error of the proposed design under different input voltages. Notably, the minimum corner errors observed at +15 and -7 sign bits are 0.45 % and 0.63 %, respectively. The significant outcome highlights that the single-switch implementation achieves optimal performance, displaying the lowest error value of 0.14%, specifically at the + 15 sign bit and operating at 1.8 V.