RT Book,_Section
T1 5-Bit Signed SRAM-Based In-Memory Computing Cell
A1 Karimpour, Faranak
A1 Pardo, F.
A1 García Lesta, Daniel
AB Hardware accelerators are critical in providing real-time processing for edge computing applications, particu-larly in the context of convolutional neural networks. A crucial challenge in this context is achieving low power consumption while maintaining an appropriate performance in terms of accuracy. This work delves into a thorough analysis of prospective architectures for the core cell of the multiply -and -accumulate function, monitoring each structure's crucial benefits and drawbacks. It includes electrical simulations comparing their performance in a 180 nm process node for 1.8 V and 3.3 V. Moreover, a process corner simulation is proposed to identify on-chip process variations in the voltage error of the proposed design under different input voltages. Notably, the minimum corner errors observed at +15 and -7 sign bits are 0.45 % and 0.63 %, respectively. The significant outcome highlights that the single-switch implementation achieves optimal performance, displaying the lowest error value of 0.14%, specifically at the + 15 sign bit and operating at 1.8 V.
PB IEEE
SN 979-8-3503-8624-0
YR 2024
FD 2024-07-08
LK https://hdl.handle.net/10347/45980
UL https://hdl.handle.net/10347/45980
LA eng
NO F. Karimpour, F. Pardo and D. García-Lesta, "5-Bit Signed SRAM-Based In-Memory Computing Cell," 2024 IEEE 24th International Conference on Nanotechnology (NANO), Gijon, Spain, 2024, pp. 126-130, doi: 10.1109/NANO61778.2024.10628891
NO Celda SRAM para computación en memoria sobre tecnología CMOS.
NO This work has received funding from projects PID2021-128009OB-C32 and TED2021-132372B-I00 from the MCIN/AEI/10.13039/501100011033 and FEDER and European Union NextGenerationEU/PRTR and the Euro- pean Regional Development Fund: Xunta de Galicia-Conseller´ıa de Cultura, Educaci´on e Ordenaci´on Universitaria Accreditation 2019–2022 ED431G- 2019/04 and Reference Competitive Group Accreditation 2021–2024, GRC2021/48, and from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 101016734.
DS Minerva
RD 29 abr 2026