Spatial Sensitivity of Silicon GAA Nanowire FETs Under Line Edge Roughness Variations

Abstract

Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However, this spatial information is paramount for the industry and academia to improve the design of variability-resistant architectures. A recently developed technique, the fluctuation sensitivity map (FSM) is used to analyze the spatial effect of the line edge roughness (LER) variability in key figures-of-merit (FoM) in silicon gate-all-around (GAA) nanowire (NW) FETs. This technique gives insight about the local sensitivity identifying the regions inducing the strongest variability into the FoM. We analyze both 22 and 10 nm gate length GAA NW FETs affected by the LER with different amplitudes (0.6, 0.7, and 0.85 nm) and correlation lengths (10 and 20 nm) using in-house 3-D quantum-corrected drift-diffusion simulation tool calibrated against experimental or Monte Carlo data. The FSM finds that the gate is the most sensitive region to LER deformations. We demonstrate that the specific location of the deformation inside the gate plays an important role in the performance and that the effect of the location is also dependent on the FoM analyzed. Moreover, there is a negligible impact on the device performance if the LER deformation occurs in the source or drain region.