Nagy, DanielEspiñeira Deus, GabrielIndalecio Fernández, GuillermoGarcía Loureiro, Antonio JesúsKalna, KarolSeoane Iglesias, Natalia2020-10-262020-10-262020D. Nagy, G. Espiñeira, G. Indalecio, A. J. García-Loureiro, K. Kalna and N. Seoane, "Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes," in IEEE Access, vol. 8, pp. 53196-53202, 2020, doi: 10.1109/ACCESS.2020.2980925.http://hdl.handle.net/10347/23424Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L G ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to L G of 16 nm offering a larger on-current (I ON ) and slightly better sub-threshold characteristics. Below L G of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (I OFF ), and the largest I ON /I OFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device bodyeng© The Author(s) 2020. Open Access. This work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/Atribución 4.0 Internacionalhttp://creativecommons.org/licenses/by/4.0/FinFETsMonte CarloSchrödinger quantum correctionNanowireNanosheetjournal article10.1109/ACCESS.2020.29809252169-3536open access