Nagy, DanielIndalecio Fernández, GuillermoGarcía Loureiro, Antonio JesúsElmessary, Muhammad A.Seoane Iglesias, Natalia2020-05-202020-05-202018Nagy, D., Indalecio, G., García-Loureiro, A. J., Elmessary, M. A., Kalna, K., and Seoane, N. (2018). FinFET versus gate-all-around nanowire FET: performance, scaling, and variability. IEEE Journal of the Electron Devices Society, 6, 332-340. https://dx.doi.org/10.1109/JEDS.2018.28043832168-6734http://hdl.handle.net/10347/22457Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred (110) channel orientation is more resilient to the MGG and LER variability in both architectures.eng© 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.Drift-diffusion (DD)Monte Carlo (MC) simulationsDensity gradient (DG) quantum correctionsSchrödinger equation based quantum correctionsSi FinFETGate-all-around (GAA) nanowire (NW) FETMetal grain granularity (MGG)Line edge roughness (LER)journal article10.1109/JEDS.2018.2804383open access