Karimpour, FaranakPardo, F.García Lesta, Daniel2026-02-192026-02-192024-07-08F. Karimpour, F. Pardo and D. García-Lesta, "5-Bit Signed SRAM-Based In-Memory Computing Cell," 2024 IEEE 24th International Conference on Nanotechnology (NANO), Gijon, Spain, 2024, pp. 126-130, doi: 10.1109/NANO61778.2024.10628891979-8-3503-8624-0https://hdl.handle.net/10347/45980Celda SRAM para computación en memoria sobre tecnología CMOS.Hardware accelerators are critical in providing real-time processing for edge computing applications, particu-larly in the context of convolutional neural networks. A crucial challenge in this context is achieving low power consumption while maintaining an appropriate performance in terms of accuracy. This work delves into a thorough analysis of prospective architectures for the core cell of the multiply -and -accumulate function, monitoring each structure's crucial benefits and drawbacks. It includes electrical simulations comparing their performance in a 180 nm process node for 1.8 V and 3.3 V. Moreover, a process corner simulation is proposed to identify on-chip process variations in the voltage error of the proposed design under different input voltages. Notably, the minimum corner errors observed at +15 and -7 sign bits are 0.45 % and 0.63 %, respectively. The significant outcome highlights that the single-switch implementation achieves optimal performance, displaying the lowest error value of 0.14%, specifically at the + 15 sign bit and operating at 1.8 V.eng© 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.book part10.1109/NANO61778.2024.10628891open access