Seoane Iglesias, NataliaMartínez, A.2025-01-232025-01-232013-09-121089-7550https://hdl.handle.net/10347/38952In this paper we present a 3D quantum transport simulation study of source-to-drain tunnelling in gate-all-around Si nanowire transistors by using the non-equilibrium Green's function approach. The impact of the channel length, device cross-section, and drain and gate applied biases on the source-to-drain tunnelling is examined in detail. The overall effect of tunnelling on the ID-VG characteristics is also investigated. Tunnelling in devices with channel lengths of 10 nm or less substantially enhances the off-current. This enhancement is more important at high drain biases and at larger cross-sections where the sub-threshold slope is substantially degraded. A less common effect is the increase in the on-current due to the tunnelling which contributes as much as 30% of the total on-current. This effect is almost independent of the cross-section, and it depends weakly on the studied channel lengths.engAttribution-NonCommercial-NoDerivatives 4.0 Internationalhttp://creativecommons.org/licenses/by-nc-nd/4.0/Electronic transportElectron densityElectrical properties and parametersField effect transistorsCurrent-voltage characteristicComputer simulationNanowiresLeptonsElectron tunnelingPotential energy barrier3307 Tecnología electrónicajournal article10.1063/1.4820390open access