Pereira Rial, ÓscarGarcía Lesta, DanielVaquero Otal, LorenzoLópez Martínez, PaulaBrea Sánchez, Víctor ManuelCabello Ferrer, Diego2026-02-182026-02-182024-05-19Ó. Pereira-Rial, D. García-Lesta, L. Vaquero, P. López, V. M. Brea and D. Cabello, "Live Demonstration: 5-bit signed SRAM-based DNN CIM for Image Recognition," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-1, doi: 10.1109/ISCAS58744.2024.10558078979-8-3503-3099-1https://hdl.handle.net/10347/45961Demostrador de reconocimiento de imágenes sobre un circuito integrado CMOS con arquitectura de computación en memoria basado en SRAM.This live demonstration shows a mixed-signal Computer In Memory (CIM) macro deep neural network (DNN) integrated circuit in 180 nm CMOS technology for image recognition. Images are coded as pulse width modulation (PWM) signals. DNN weights are stored as voltages in 6T-SRAM memories which drive current sources inside every multiplier. Multipliers are arranged within processing elements laid down in a 2D mesh suitable for image processing. The power consumption per multiplier of the CIM macro is of 0.22 µW, below state-of-the-art competitors following the same multiply and accumulate (MAC) principle.eng© 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.Investigaciónbook part10.1109/ISCAS58744.2024.10558078open access