RT Journal Article
T1 Performance analysis of massively parallel embedded hardware architectures for retinal image processing
A1 Nieto Lareo, Alejandro Manuel
A1 Brea Sánchez, Víctor Manuel
A1 López Vilariño, David
A1 Osorio, Roberto R.
K1 Active Contour
K1 Retinal Image
K1 External Memory
K1 Initial Contour
K1 Processor Array
AB This paper examines the implementation of a retinal vessel tree extraction technique on different hardware platforms and architectures. Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of low-level tasks in order to meet the accuracy requirements. In some applications, this might compromise computing speed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on different hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays (FPGA)
PB Springer
SN 1687-5176
YR 2011
FD 2011
LK http://hdl.handle.net/10347/17715
UL http://hdl.handle.net/10347/17715
LA eng
NO Nieto, A., Brea, V., Vilariño, D., & Osorio, R. (2011). Performance analysis of massively parallel embedded hardware architectures for retinal image processing. EURASIP Journal On Image And Video Processing, 2011(1). doi: 10.1186/1687-5281-2011-10
NO This work is funded by Xunta de Galicia under the projects 10PXIB206168PR and 10PXIB206037PR and the program Maria Barbeito
DS Minerva
RD 28 abr 2026