RT Journal Article
T1 Iterative algorithm and architecture for exponential, logarithm, powering, and root extraction
A1 Vázquez Álvarez, Álvaro
A1 Díaz Bruguera, Javier
K1 Elementary functions computation
K1 Digit–recurrence algorithms
K1 High–radix algorithms
K1 Floating–point representation
AB An algorithm and architecture for powering computation and root extraction, with fixed–point and floating–point exponents, is presented in this paper. The algorithm is based on an optimized iterative sequence of parallel and/or overlapped operations: (1) reciprocal, (2) high–radix digit–recurrence logarithm, (3) left–to–right carry–free multiplication and (4) high–radix on–line exponential. A redundant number system is used to allow for the overlapping of the different operations of the algorithm. As the logarithm and exponential are part of the sequence of operations, some minor changes are made to allow for the independent computation of the logarithm and exponential functions. A sequential implementation of the algorithm is proposed and the execution times and hardware requirements are estimated for single and double-precision floating-point computations. These estimates are obtained for several radices, according to an approximate model for the delay and area of the main logic blocks, and help to determine the radix values which lead to the most efficient implementations
PB IEEE
SN 0018-9340
SN 1557-9956
YR 2013
FD 2013-09
LK https://hdl.handle.net/10347/46040
UL https://hdl.handle.net/10347/46040
LA eng
NO Vazquez, A., Bruguera, J.D. (2013). Iterative Algorithm and Architecture for Exponential, Logarithm, Powering and Root Extraction. "IEEE Transactions on Computers", 62(9), 1721-1731
NO Work supported in part by Ministry of Science and Innovation of Spain, co-funded by the FEDER funds of the European Union, under contract TIN2010-17541.
NO Work supported in part by the Xunta de Galicia, Program for Consolidation of Competitive Research Groups ref. 2010/28.
DS Minerva
RD 19 may 2026