RT Journal Article
T1 FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
A1 Nagy, Daniel
A1 Indalecio Fernández, Guillermo
A1 García Loureiro, Antonio Jesús
A1 Elmessary, Muhammad A.
A1 Seoane Iglesias, Natalia
K1 Drift-diffusion (DD)
K1 Monte Carlo (MC) simulations
K1 Density gradient (DG) quantum corrections
K1 Schrödinger equation based quantum corrections
K1 Si FinFET
K1 Gate-all-around (GAA) nanowire (NW) FET
K1 Metal grain granularity (MGG)
K1 Line edge roughness (LER)
AB Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred (110) channel orientation is more resilient to the MGG and LER variability in both architectures.
PB IEEE
SN 2168-6734
YR 2018
FD 2018
LK http://hdl.handle.net/10347/22457
UL http://hdl.handle.net/10347/22457
LA eng
NO Nagy, D., Indalecio, G., García-Loureiro, A. J., Elmessary, M. A., Kalna, K., and Seoane, N. (2018). FinFET versus gate-all-around nanowire FET: performance, scaling, and variability. IEEE Journal of the Electron Devices Society, 6, 332-340. https://dx.doi.org/10.1109/JEDS.2018.2804383
NO This work was supported in part by the Spanish Government under Project TIN2013-41129-P and Project TIN2016-76373-P, in part by the Xunta de Galicia and FEDER under Grant GRC2014/008, in part by the Consellería de Cultura, Educación e Ordenación Universitaria (accreditation 2016–2019) under Grant ED431G/08, and in part by the Spanish Ministry of Economyand Competitiveness and FEDER under Grant TEC2014-59402-JIN. The work of G. Indalecio was supported by the Programa de Axudas Etapa Posdoutoral da Xunta deGalicia under Grant 2017/077
DS Minerva
RD 24 abr 2026