RT Journal Article
T1 Fast radix-10 multiplication using redundant BCD codes
A1 Vázquez Álvarez, Álvaro
A1 Antelo Suárez, Elisardo
A1 Díaz Bruguera, Javier
K1 Parallel multiplication
K1 Decimal hardware
K1 Overloaded BCD representation
K1 Redundant excess-3 code
K1 Redundant arithmetic
AB We present the algorithm and architecture of a BCD parallel multiplier that exploits some properties of two different redundant BCD codes to speedup its computation: the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition, new techniques are developed to reduce significantly the latency and area of previous representative high-performance implementations. Partial products are generated in parallel using a signed-digit radix-10 recoding of the BCD multiplier with the digit set [-5, 5], and a set of positive multiplicand multiples (0X, 1X, 2X, 3X, 4X, 5X) coded in XS-3. This encoding has several advantages. First, it is a self-complementing code, so that a negative multiplicand multiple can be obtained by just inverting the bits of the corresponding positive one. Also, the available redundancy allows a fast and simple generation of multiplicand multiples in a carry-free way. Finally, the partial products can be recoded to the ODDS representation by just adding a constant factor into the partial product reduction tree. Since the ODDS uses a similar 4-bit binary encoding as non-redundant BCD, conventional binary VLSI circuit techniques, such as binary carry-save adders and compressor trees, can be adapted efficiently to perform decimal operations. To show the advantages of our architecture, we have synthesized a RTL model for 16×16-digit and 34×34-digit multiplications and performed a comparative survey of the previous most representative designs. We show that the proposed decimal multiplier has an area improvement roughly in the range 20-35 percent for similar target delays with respect to the fastest implementation
PB IEEE
SN 0018-9340
SN 1557-9956
YR 2014
FD 2014-08
LK https://hdl.handle.net/10347/46038
UL https://hdl.handle.net/10347/46038
LA eng
NO Vázquez, Á., Antelo, E., Bruguera, J. D. (2014). Fast Radix-10 Multiplication Using Redundant BCD Codes. "IEEE Transactions on Computers", 63(8), 1902-1914
NO Work supported in part by Ministry of Science and Innovation of Spain, co-funded by the European Regional Development Fund (ERDF/FEDER), under contract TIN2010-17541
NO Work supported in part by the Xunta de Galicia under contracts 2010/28 and CN2012/151
DS Minerva
RD 18 may 2026