RT Journal Article
T1 Ultralow power voltage reference circuit for implantable devices in standard CMOS technology
A1 Pereira Rial, Óscar
A1 López Martínez, Paula
A1 Carrillo, Juan M.
A1 Brea Sánchez, Víctor Manuel
A1 Cabello Ferrer, Diego
K1 Design methodology
K1 Picowatt
K1 Subthreshold
K1 Trim‐free
K1 Ultralow power
K1 Voltage reference
AB An ultralow power CMOS voltage reference for body implantable devices is presented in this paper. The circuit core consists of only regular threshold voltage PMOS transistors, thus leading to a very reduced output voltage dispersion, defined as σ/μ, and extremely low power consumption. A mathematical model of the generated reference voltage was obtained by solving circuit equations, and its numerical solution has been validated by extensive electrical simulations using a commercial circuit simulator. The proposed solution incorporates a passive RC low‐pass filter, to enhance power supply rejection (PSR) over a wide frequency range, and a speed‐up section, to accelerate the switching‐on of the circuit. The prototype was implemented in 0.18 μm standard CMOS technology and is able to operate with supply voltages ranging from 0.7 to 1.8 V providing a measured output voltage value of 584.2 mV at the target temperature of 36° C. The measured σ/μ dispersion of the reference voltage generated is 0.65% without the need of trimming. At the minimum supply of 0.7 V, the experimental power consumption is 64.5 pW, while the measured PSR is kept below –60 dB from DC up to the MHz frequency range
PB Wiley
YR 2019
FD 2019
LK http://hdl.handle.net/10347/24640
UL http://hdl.handle.net/10347/24640
LA eng
NO Pereira-Rial Ó, López P, Carrillo JM, Brea VM, Cabello D. Ultralow powervoltage reference circuit for implantable devices in standard CMOS technology. Int J Circ Theor Appl. 2019;47:991–1005. https://doi.org/10.1002/cta.2643
NO This is the peer reviewed version of the following article: Óscar Pereira-Rial, Paula López, Juan M. Carrillo, Victor M. Brea and Diego Cabello (2019) Ultralow power voltage reference circuit for implantable devices in standard CMOS technology. International journal of circuit theory and applications, 47 (7), 991-1005, which has been published in final form at https://doi.org/10.1002/cta.2643. This article may be used for non-commercial purposes in accordance with Wiley Terms and Conditions for Use of Self-Archived Versions
NO This work has been partially funded by the Spanish government projects TEC2015‐66878‐C3‐3‐R (MINECO/FEDER) and RTI2018‐097088‐B‐C32 (FEDER), by the Xunta de Galicia under project ED431C2017/69, by the Consellería de Cultura, Educación e Ordenación Universitaria (accreditation 2016‐2019, ED431G/08 and reference competitive group 2017‐2020, ED431C 2017/69), by the Junta de Extremadura R&D Plan, and the European Fund for Regional Development (EFRD) under Grant IB18079
DS Minerva
RD 24 abr 2026