RT Journal Article
T1 An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing
A1 Pereira Rial, Óscar
A1 López Martínez, Paula
A1 Carrillo, Juan M.
A1 Brea Sánchez, Víctor Manuel
A1 Cabello Ferrer, Diego
K1 adaptive biasing
K1 analog integrated circuits
K1 capacitor-less LDO
K1 low-power
K1 nano-ampere
K1 super source follower
AB This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 - 11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO’s error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio.
PB IEEE
SN 1558-3791
YR 2021
FD 2021-11-25
LK http://hdl.handle.net/10347/32646
UL http://hdl.handle.net/10347/32646
LA eng
NO Ó. Pereira-Rial, P. López, J. M. Carrillo, V. M. Brea and D. Cabello, "An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, pp. 844-848, March 2022, doi: 10.1109/TCSII.2021.3130674
DS Minerva
RD 28 abr 2026