RT Journal Article
T1 Improved design of high-performance parallel decimal multipliers
A1 Vázquez Álvarez, Álvaro
A1 Antelo Suárez, Elisardo
A1 Montuschi, Paolo
K1 Decimal multiplication
K1 Parallel multiplication
K1 Decimal carry-save addition
K1 Decimal codings
AB The new generation of high-performance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multipliers. In this paper, we describe the architectures of two parallel decimal multipliers. The parallel generation of partial products is performed using signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a decimal multioperand carry-save addition algorithm that uses unconventional (non BCD) decimal-coded number systems. We further detail these techniques and present the new improvements to reduce the latency of the previous designs, which include: optimized digit recoders for the generation of 2n-tuples (and 5-tuples), decimal carry-save adders (CSAs) combining different decimal-coded operands, and carry-free adders implemented by special designed bit counters. Moreover, we detail a design methodology that combines all these techniques to obtain efficient reduction trees with different area and delay trade-offs for any number of partial products generated. Evaluation results for 16-digit operands show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix--8 parallel binary multipliers and outperform the figures of previous alternatives for decimal multiplication
PB IEEE
SN 0018-9340
SN 1557-9956
YR 2010
FD 2010-05-01
LK https://hdl.handle.net/10347/46064
UL https://hdl.handle.net/10347/46064
LA eng
NO Vazquez, A., Antelo, E., Montuschi, P. (2010). Improved Design of High-Performance Parallel Decimal Multipliers. "IEEE Transactions on Computers", 59(5), 679-693
NO This work was supported in part by the Ministry of Education and Science of Spain under contract TIN 2007-67537-C03
NO The authors would also like to thank IBM Germany R&D for their support.
DS Minerva
RD 24 abr 2026