RT Dissertation/Thesis
T1 Dynamically reconfigurable architecture for embedded computer vision systems
A1 Nieto Lareo, Alejandro Manuel
K1 computer vision
K1 architecture
K1 reconfigurable
K1 embedded
K1 performance
AB The objective of this research work is to design, develop and implement a new architecture which integrates on the same chip all the processing levels of a complete Computer Vision system, so that the execution is efficient without compromising the power consumption while keeping a reduced cost. For this purpose, an analysis and classification of different mathematical operations and algorithms commonly used in Computer Vision are carried out, as well as a in-depth review of the image processing capabilities of current-generation hardware devices. This permits to determine the requirements and the key aspects for an efficient architecture. A representative set of algorithms is employed as benchmark to evaluate the proposed architecture, which is implemented on an FPGA-based system-on-chip. Finally, the prototype is compared to other related approaches in order to determine its advantages and weaknesses.
YR 2013
FD 2013-02-11
LK http://hdl.handle.net/10347/7283
UL http://hdl.handle.net/10347/7283
LA eng
DS Minerva
RD 28 abr 2026