RT Book,_Section
T1 Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree
A1 Vázquez Álvarez, Álvaro
A1 Antelo Suárez, Elisardo
AB We present a novel method for hardware design of combined binary/decimal multi-operand adders. More specifically, we apply this method to architectures based on binary CSA (carry-save adder) trees, which are of interest for VLSI implementation of high performance multipliers and other low latency arithmetic units. A remarkable feature of the proposed method is that it allows the reuse of any binary CSA for computing the sum of BCD operands. Decimal corrections are performed in parallel, separately from the computation of the binary sum, such that the layout of the binary carry-save adder does not require any further rearrangement. As a result, the latency of the binary operation is unaffected by the incorporation of hardware support for decimal, while the latency for the decimal mode is close to the latency figures of dedicated decimal multi-operand adders. We show that our combined architecture is competitive in terms of area and delay with respect to other representative proposals, and that it has a more regular layout when implemented in a submicron VLSI technology.
PB IEEE
SN 978-1-4244-9722-5
SN 978-1-4244-9721-8
SN 1058-6393
YR 2010
FD 2010-11
LK https://hdl.handle.net/10347/46227
UL https://hdl.handle.net/10347/46227
LA eng
NO Vázquez, A., & Antelo, E. (2010). Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree. Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, 1685-1689.
NO This work is supported in part by the Ministry of Education and Science of Spain under contract TIN 2007-67537-C03
DS Minerva
RD 24 abr 2026