RT Journal Article
T1 Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
A1 Espiñeira, Gabriel
A1 Nagy, Daniel
A1 Kalna, K.
A1 Indalecio Fernández, Guillermo
A1 García Loureiro, Antonio Jesús
A1 Seoane Iglesias, Natalia
K1 FinFETs
K1 Gate-all-around nanowire FET
K1 Gate edge roughness
K1 Variability
AB The effect of gate edge roughness (GER) in the sub-threshold region is studied for two state-of-the-art architectures: a 10.7-nm Si FinFET and a 10-nm Si gateall-around (GAA) nanowire (NW) FET using an in-house 3D quantum-corrected drift-diffusion simulation tool. The GER is applied to the device gate using the characteristic values of root-mean-square amplitude and correlation length (CL). The GER-induced variability results in a standard deviation (σ) for the threshold voltage (VT) of 7 mV for the FinFET when CL/Gate Perimeter = 0.66 and RMS = 0.80 nm, which is 20% greater than that of the GAA NW FET. GER is a less damaging source of variability than metal grain granularity (MGG), line edge roughness (LER), and random dopants (RD) for both devices. When compared to LER variations, σVT due to the GER is 62% and 86% lower for the FinFET and GAA NW FET, respectively. However, although GER affects the FinFET more than the GAA NW FET, the combined variability effect of GER, MGG, LER, and RD (σVT,comb) on the FinFET is 30 mV, a value approximately 50% smaller than that of the GAA NW FET.
PB IEEE
SN 1558-0563
YR 2019
FD 2019-02-21
LK https://hdl.handle.net/10347/38744
UL https://hdl.handle.net/10347/38744
LA eng
NO Espiñeira, G., Nagy, D., Indalecio, G., García-Loureiro, A. J., Kalna, K. and Seoane, N. (2019). Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET. “IEEE Electron Device Letters”, vol. 40(4),510-513. doi: 10.1109/LED.2019.2900494
DS Minerva
RD 24 abr 2026