RT Dissertation/Thesis
T1 New hardware support transactional memory and parallel debugging in multicore processors
A1 Orosa Nogueira, Lois
K1 Transactional Memory
K1 Signatures
K1 Debugging
K1 Hardware
K1 Flexible
AB This thesis contributes to the area of hardware support for parallel programming by introducing new hardware elements in multicore processors, with the aim of improving the performance and optimize new tools, abstractions and applications related with parallel programming, such as transactional memory  and data race detectors. Specifically, we configure a hardware transactional memory system with signatures as part of the hardware support, and we develop a new hardware filter for reducing the signature size. We also develop the first hardware asymmetric data race detector (which is also able to tolerate them), based also in hardware signatures. Finally, we propose a new module of hardware signatures that solves some of the problems that we found in the previous tools related with the lack of flexibility in hardware signatures.
YR 2013
FD 2013-10-29
LK http://hdl.handle.net/10347/9338
UL http://hdl.handle.net/10347/9338
LA eng
DS Minerva
RD 29 abr 2026