RT Book,_Section
T1 Live Demonstration: 5-bit signed SRAM-based DNN CIM for Image Recognition
A1 Pereira Rial, Óscar
A1 García Lesta, Daniel
A1 Vaquero Otal, Lorenzo
A1 López Martínez, Paula
A1 Brea Sánchez, Víctor Manuel
A1 Cabello Ferrer, Diego
AB This live demonstration shows a mixed-signal Computer In Memory (CIM) macro deep neural network (DNN) integrated circuit in 180 nm CMOS technology for image recognition. Images are coded as pulse width modulation (PWM) signals. DNN weights are stored as voltages in 6T-SRAM memories which drive current sources inside every multiplier. Multipliers are arranged within processing elements laid down in a 2D mesh suitable for image processing. The power consumption per multiplier of the CIM macro is of 0.22 µW, below state-of-the-art competitors following the same multiply and accumulate (MAC) principle.
PB IEEE
SN 979-8-3503-3099-1
YR 2024
FD 2024-05-19
LK https://hdl.handle.net/10347/45961
UL https://hdl.handle.net/10347/45961
LA eng
NO Ó. Pereira-Rial, D. García-Lesta, L. Vaquero, P. López, V. M. Brea and D. Cabello, "Live Demonstration: 5-bit signed SRAM-based DNN CIM for Image Recognition," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-1, doi: 10.1109/ISCAS58744.2024.10558078
NO Demostrador de reconocimiento de imágenes sobre un circuito integrado CMOS con arquitectura de computación en memoria basado en SRAM.
NO This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 101016734; and the European Union (European Regional Development Fund): from the Xunta de Galicia-Conselleria de Cultura, Educación e Ordenación Universitaria Accreditation 2019–2022 ED431G-2019/04 and Reference Competitive Group Accreditation 2021–2024, GRC2021/48, and from the Spanish Ministry of Science, Innovation and Universities under grant PID2021-128009OB-C32
DS Minerva
RD 23 abr 2026