Live Demonstration: 5-bit signed SRAM-based DNN CIM for Image Recognition

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dc.contributor.affiliationUniversidade de Santiago de Compostela. Centro de Investigación en Tecnoloxías Intelixentes da USC (CiTIUS)
dc.contributor.authorPereira Rial, Óscar
dc.contributor.authorGarcía Lesta, Daniel
dc.contributor.authorVaquero Otal, Lorenzo
dc.contributor.authorLópez Martínez, Paula
dc.contributor.authorBrea Sánchez, Víctor Manuel
dc.contributor.authorCabello Ferrer, Diego
dc.date.accessioned2026-02-18T10:22:53Z
dc.date.available2026-02-18T10:22:53Z
dc.date.issued2024-05-19
dc.descriptionDemostrador de reconocimiento de imágenes sobre un circuito integrado CMOS con arquitectura de computación en memoria basado en SRAM.
dc.description.abstractThis live demonstration shows a mixed-signal Computer In Memory (CIM) macro deep neural network (DNN) integrated circuit in 180 nm CMOS technology for image recognition. Images are coded as pulse width modulation (PWM) signals. DNN weights are stored as voltages in 6T-SRAM memories which drive current sources inside every multiplier. Multipliers are arranged within processing elements laid down in a 2D mesh suitable for image processing. The power consumption per multiplier of the CIM macro is of 0.22 µW, below state-of-the-art competitors following the same multiply and accumulate (MAC) principle.
dc.description.sponsorshipThis project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 101016734; and the European Union (European Regional Development Fund): from the Xunta de Galicia-Conselleria de Cultura, Educación e Ordenación Universitaria Accreditation 2019–2022 ED431G-2019/04 and Reference Competitive Group Accreditation 2021–2024, GRC2021/48, and from the Spanish Ministry of Science, Innovation and Universities under grant PID2021-128009OB-C32
dc.identifier.citationÓ. Pereira-Rial, D. García-Lesta, L. Vaquero, P. López, V. M. Brea and D. Cabello, "Live Demonstration: 5-bit signed SRAM-based DNN CIM for Image Recognition," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 2024, pp. 1-1, doi: 10.1109/ISCAS58744.2024.10558078
dc.identifier.doi10.1109/ISCAS58744.2024.10558078
dc.identifier.isbn979-8-3503-3099-1
dc.identifier.urihttps://hdl.handle.net/10347/45961
dc.language.isoeng
dc.publisherIEEE
dc.relation.projectIDinfo:eu-repo/grantAgreement/EC/H2020/101016734
dc.relation.projectIDinfo:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2021-2023/PID2021-128009OB-C32/ES/INTELIGENCIA ARTIFICIAL EN EL BORDE: SOLUCIONES EMBEBIDAS DE BAJO CONSUMO DE POTENCIA
dc.relation.publisherversionhttps://doi.org/10.1109/ISCAS58744.2024.10558078
dc.rights© 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
dc.rights.accessRightsopen access
dc.subject.classificationInvestigación
dc.titleLive Demonstration: 5-bit signed SRAM-based DNN CIM for Image Recognition
dc.typebook part
dc.type.hasVersionAM
dspace.entity.typePublication
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